Acer 486 Manuel d'utilisateur Page 37

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Am486
®
Microprocessor PCI Customer Development Platform
2-7
Board Restrictions
Using a PCI chipset with the Am486 microprocessor is a fast and effective way
to design a working system, but the system’s features can be limited by the
chipset’s capabilities.
The chipset used in the PCI CDP supports 5-V PCI 2.0 devices only. Three
devices are supported: the onboard Ethernet controller and two PCI slots.
Except for the adjustable CPU supply voltage and 3.3-V Ethernet controller, the
PCI CDP uses 5-V power throughout. (The Am486 microprocessor provides 5-
V-tolerant I/O.)
The chipset does not directly support ROM or Flash memory devices except for
the boot ROM. It is possible to implement Flash memory on the DRAM, PCI
or ISA bus, but the chipset only allows booting from the boot ROM. ISA-bus
Flash memory is limited to 1 Mbyte because of addressing considerations.
The PCI CDP implements two banks of execute-in-place (EIP) Flash memory
in place of one DRAM bank. Flash memory timing requirements limit the
chipset’s DRAM interface to its Fast (not Fastest) speed when the Flash memory
is used. This is equivalent to using 70-ns fast-page-mode (FPM) DRAM.
The chipset allows only three banks of DRAM to be attached without external
buffers. Buffering the DRAM adds one wait state and reduces the available
performance. “DRAM Main Memory (P7)” on page 2-20 describes additional
DRAM device and configuration limits.
The ISA peripherals provided by the M1487 chip are configured for standard
PC-AT compatibility, so there is not much flexibility in assigning interrupts and
DMA channels.
The PCI CDP does not implement OnNow or Advanced Configuration and
Power Interface (ACPI) power management.
Board Features
The remainder of this chapter describes the features of the PCI CDP. The number
in parentheses following each heading indicates the part’s location in Figure 2-3
on page 2-5. In addition, other locations referenced can be found in the figure.
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