Acer 486 Manuel d'utilisateur télécharger pdf (Page 53)

Am486

Microprocessor PCI Customer Development Platform

2-23

ISA Flash Memory (F20)

The PCI CDP includes 1 Mbyte of 16-bit wide AMD Flash memory soldered onto

the board and located logically on the ISA Bus. A Vantis MACH programmable

logic device is used to control the interface between the ISA bus and the Flash

device. This provides an example of how a small amount of ISA Flash memory

might be implemented in customer designs.

The ISA Flash memory employs one Am29F800 top-sector boot block Flash

memory chip (part U58). This device occupies ISA memory space from address

F00000h to FFFFFFh. See Figure 2-6 on page 2-24. Software should access this

space in 16-bit words on even addresses.

Software can enable this ISA memory space by setting bit 3 of the chipset’s ROM

Function Register, index 12h. This disables DRAM access in the 1-Mbyte range

from F00000h to FFFFFFh, allowing access to the ISA memory space instead. If

bit 3 of index 12h is clear, access to the ISA Flash memory space is allowed only

if 15 Mbytes or less of DRAM is installed.

The Flash device is configured in word mode, so only 16-bit access is allowed.

The ISA address signals are routed so that ISA address bit A1 is routed to bit A0

on the Flash device, so it can only be addressed on even word boundaries. When

generating Flash command sequences, multiply the Flash address by two to

generate the correct ISA address. For example, writing address F00AAAh asserts

555h (AAAh ÷ 2) on the Flash device’s address pins.

The Am29F800 can be programmed using the JDEC single-power-supply Flash

standard command set. See the Am29F800 documentation for details. Software

for using Flash memory is provided with the PCI CDP. See the readme file on the

diskette that came with your kit for information about available utilities.

ISA space is limited to 16 Mbytes, and because the chipset provides limited support

for mapping ISA memory windows over DRAM, only 1 Mbyte of Flash memory

is provided. However, in a customer design with a small amount of DRAM, a larger

ISA Flash memory space can be situated between the top of DRAM and the 16

Mbyte ISA address limit. Note that access to memory on the ISA bus is relatively

slow when compared to DRAM or PCI bus transactions. See “EIP Flash Memory

(L21)” on page 2-25 for another approach.

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Acer 486 Manuel d'utilisateur Page 53